benim sattığım ram mi

1GB
Non-ECC optimized pinout
184-pin, dual in-line memory modules (DIMM)
Gold leads
Phase-lock loop (PLL) clock driver to reduce loading
VDD = +2.5V �0.2V, VDDQ = +2.5V �0.2V
VDDSPD = +2.5V to +3.3V
2.5V I/O (SSTL_2 compatible)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-aligned with data for WRITEs
Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture
Differential clock inputs (CK0 and CK0#)
Four internal banks for concurrent operation
Programmable burst lengths: 2, 4, or 8
Auto precharge option
Auto Refresh and Self Refresh Modes
15.6µs maximum average periodic refresh interval


buözellikler onunlauyuyor mu? :d